export default  {
	"title": '计算机系统结构_在线3',
	"testId": '83488',
	"praxiseList": [
		{
			"id": 127234,
			"title": "下面有关MIPS架构的lw/sw指令数据通路设计的叙述，哪些是正确的？\n1.在lw/sw指令数据通路中，一定有一个符号扩展部件用于偏移量的扩展\n2.在lw/sw指令数据通路中，ALU的控制信号一定为“add”（即ALU做加法）\n3.寄存器堆的“写使能（RegWrite)”信号在lw指令执行时为“1”，在sw指令执行时为“0”\n4.数据存储器的“写使能(MemWrite”信号在lw指令执行时为“0”，在sw指令执行时为“1”",
			"options": "[\"1，2\",\"2，4\",\"全对\",\"1，3\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127235,
			"title": "某计算机指令集中包含RR型运算指令（源操作数和目的操作数都是寄存器）、取数指令load,、存数指令store,、条件分支指令branch和直接跳转指令jump。 如果采用单周期数据通路实现该指令系统，各主要功能部件的操作时间为：指令存储器和数据存储器都是2ns; ALU和加法器都是1ns; 寄存器文件的读和写都是0.5ns. 在不考虑多路选择器、控制器、PC、符号扩展单元和传输延迟的情况下，该计算机的时钟周期至少为多少？",
			"options": "[\"5ns\",\"7ns\",\"8ns\",\"6ns\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127236,
			"title": "以下是一段MIPS指令序列：\naddi ﹩t1, ﹩zero, 20    #R[﹩t1]<-20\nlw    ﹩t2, l2(﹩a0)       #R[﹩t2]<-M[R[﹩a0]+12]\nadd  ﹩v0, ﹩t1, ﹩t2      #R[﹩v0]<-R[﹩t1]+R[﹩t2]\n以上指令序列中，第1和第3，第2和第3条指令之间发生数据相关。假定采用“取指、译码/取数、执行、访存、写回”这种5段流水线方式，并控制在时钟的前半周期写寄存器堆，后半周期读寄存器堆，那么不采用“转发”技术时，需要在第3条指令前加入多少条空操作（nop）指令才能使这段程序不发生数据冒险？",
			"options": "[\"2\",\"4\",\"3\",\"1\"]",
			"answer": "1",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127237,
			"title": "以下关于流水线数据通路的描述中，错误的是？",
			"options": "[\"在没有阻塞的情况下，PC的值在每个时钟周期都会改变\",\"控制信号仅作用在功能部件上，时钟信号仅作用在流水段寄存器上\",\"在有阻塞的情况下，一条指令可以停留在某个功能部件上超过一个时钟周期\",\"每个流水段由执行指令子功能的功能部件和流水段寄存器组成\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127238,
			"title": "以下关于流水段的功能部件的描述中，错误的是？",
			"options": "[\"寄存器写口只能在指令结束时的“写回”阶段被使用\",\"所有功能部件都要用组合逻辑实现\",\"每个功能部件在每条指令中都只被使用一次\",\"同一个功能部件可以在不同的流水段中被使用\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127239,
			"title": "以下给定的情况中，不会引起指令流水线阻塞的是？",
			"options": "[\"访存冲突\",\"cache缺失\",\"指令数据相关\",\"执行空操作指令\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127240,
			"title": "以下情况中，不会引起指令流水线阻塞的是？",
			"options": "[\"TLB缺失\",\"数据旁路（转发）\",\"条件转移\",\"高速缓存不命中\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127241,
			"title": "以下是关于结构冒险的叙述：\n1. 结构冒险是指同时有多条指令使用同一个资源\n2. 避免结构冒险的基本做法是使每个指令在相同流水段中使用相同的部件\n3.  重复设置功能部件可以避免结构冒险\n4. 数据cache和代码cache分离可解决两条指令同时分别访问数据和指令的冒险\n以上叙述中，正确的有？",
			"options": "[\"1，3，4\",\"1，2，3\",\"1，2，4\",\"全部\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127242,
			"title": "以下是关于数据冒险的叙述：\n1. 数据冒险是指后面指令用到的数据还未来得及由前面指令产生\n2. 在发生数据冒险的指令之间插入空操作指令能避免数据冒险\n3. 采用转发（旁路）技术可以解决一部分数据冒险现象\n4. 通过编译器调整指令顺序可解决部分数据冒险\n以上叙述中，正确的有（）。",
			"options": "[\"全部\",\"1，2，4\",\"1，2，3\",\"1，3，4\"]",
			"answer": "1",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127243,
			"title": "以下是一段MIPS指令序列：\nloop:add    ﹩t1, ﹩s3, ﹩s3    #R[﹩t1]<-R[﹩s3]+R[﹩s3]\n       add    ﹩t1, ﹩t1, ﹩t1      #R[﹩t1]<-R[﹩t1]+R[﹩t1]\n       lw      ﹩t0, 0(﹩t1)          #R[﹩t0]<-M[R[﹩t1]+0]\n       bne     ﹩t0, ﹩s5, exit    #if(R[﹩t0]!=R[﹩s5]) then go to exit\n       add     ﹩s3, ﹩s3, ﹩s4   #R[﹩s3]<-R[﹩s3]+R[﹩s4]\n       j          loop                   #go to loop\nexit:\n以上指令序列中，第（）条指令产生了一个分支控制冒险。",
			"options": "[\"5\",\"4\",\"6\",\"2\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127244,
			"title": "以下是一条MIPS指令序列：\nadd ﹩t1, ﹩t0, ﹩t1     #R[﹩t1]<-R[﹩t0]+R[﹩t1]\nlw    ﹩t0, 0(﹩t1)        #R[﹩t0]<-M[R[﹩t1]+0]\nbne  ﹩t0, ﹩s5, exit    #if(R[﹩t0]!=R[﹩s5]) then go to exit\nadd  ﹩s3, ﹩s5, ﹩s4   #R[﹩s3]<-R[﹩s5]+R[﹩s4]\nexit:\n以上指令序列中，（   ）指令之间产生数据相关。",
			"options": "[\"1和2，1和3\",\"1和2，2和3，3和4\",\"1和2，2和3\",\"1和2，1和3，2和3\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127245,
			"title": "响应外部中断的过程中，中断隐指令（硬件）完成的操作，除了保护断点外，还包括（        ）。\n1. 关中断          2. 保存通用寄存器的内容         3. 形成中断服务程序入口地址并送PC",
			"options": "[\"1，2，3\",\"仅1和3\",\"仅2和3\",\"仅1和2\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127246,
			"title": "中断处理和函数（子程序）调用都需要压栈以保护现场，中断处理一定会保存而子程序调用不需要保存其内容的是（   ）。",
			"options": "[\"通用数据寄存器\",\"通用地址寄存器\",\"程序计数器，如PC\",\"程序状态字寄存器\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127247,
			"title": "以下I/O 控制方式中，主要由硬件而不是软件实现数据传送的方式是（   ）。",
			"options": "[\"无条件程序控制方式\",\"程序查询方式\",\"DMA方式\",\"中断方式\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127248,
			"title": "某计算机CPU主频为500MHz，CPI为5. 假定某外设的数据传输率为0.5MB/s，采用中断方式与主机进行数据传送，每次数据传输的单位为32位，对应的中断服务程序包含18条指令，中断响应等其他开销相当于2条指令的执行时间。中断方式下，CPU用于该外设I/O的时间占整个CPU时间的百分比是多少？",
			"options": "[\"2.5%\",\"25%\",\"1.25%\",\"5%\"]",
			"answer": "1",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127249,
			"title": "某计算机CPU主频为500MHz，CPI为5. 假定某外设的数据传输率为5MB/s，用DMA方式传送数据。假定每次DMA传送的块大小为5000B，DMA预处理和后处理的开销为500个时钟周期，则CPU用于该外设I/O的时间占整个CPU时间的百分比是多少？（假设DMA与CPU之间没有访存冲突）",
			"options": "[\"0.5%\",\"1%\",\"0.1%\",\"10%\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127250,
			"title": "在采用中断I/O 方式控制打印输出的情况下，CPU 和打印控制接口中的I/O 端口之间交换的信息不可能是？",
			"options": "[\"控制命令\",\"打印字符\",\"设备状态\",\"主存地址\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127251,
			"title": "处理外部中断时，应该由（软件）操作系统保存的是？",
			"options": "[\"块表(TLB)中的内容\",\"Cache 中的内容\",\"通用寄存器的内容\",\"程序计数器(PC)的内容\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127252,
			"title": "内部异常是指令执行过程中处理器内部发生的特殊事件，外部中断是来自处理器外部的请求事件。下列关于中断和异常情况的叙述中，错误的是？",
			"options": "[\"“整数除以0“属于内部异常\",\"“DMA传送结束“属于外部中断\",\"“存储保护出错（访存越界）“属于内部异常\",\"“访存时缺页“属于外部中断\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127253,
			"title": "下列关于多重中断系统的叙述中，错误的是？",
			"options": "[\"在一条指令执行结束前响应中断\",\"中断处理期间CPU一直处于关中断状态\",\"在保存现场和恢复现场时，必须处于关中断状态\",\"CPU通过采样中断请求信号检测中断请求\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127254,
			"title": "输入输出指令实现的数据传送通常发生在？",
			"options": "[\"输入输出设备和I\\/O端口之间\",\"I\\/O端口和I\\/O端口之间\",\"通用寄存器和I\\/O设备之间\",\"通用寄存器和I\\/O端口之间\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127255,
			"title": "采用整数边界存储技术，其主要目的是（ ）。",
			"options": "[\"节约主存空间\",\"提高数据的访问速度\",\"一个主存周期可取多条指令\",\"一个主存周期至少可取到一条指令\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127256,
			"title": "计算机使用的语言是 ( )",
			"options": "[\"专属软件范畴，与计算机体系结构无关\",\"分属于计算机系统各个层次\",\"属于用以建立一个用户的应用环境\",\"属于符号化的机器指令\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127257,
			"title": "流水计算机中将指令 Cache 和数据 Cache 分开，主要是为了（ ）。",
			"options": "[\"提高存储系统的速度\",\"增加主存容量\",\"解决功能部件冲突\",\"解决访存冲突\"]",
			"answer": "4",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127258,
			"title": "当今微型机中实现软件移植最好的方法是（ ）。",
			"options": "[\"系列机\",\"兼容机\",\"C仿真技术\",\"统一高级语言\"]",
			"answer": "1",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127259,
			"title": "当 N=16 时，能描述 4 组 4 元交换的函数是（ ）。",
			"options": "[\"C1+C2\",\"C0+C1\",\"C0+C2\",\"C2+C3\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127260,
			"title": "对计算机系统结构来说，不透明的是（ ）。",
			"options": "[\"存储器采用交叉存取还是并行存取\",\"CPU内部的数据通路的宽度是 8 位还是 16 位\",\"采用浮点数据表示还是标志符数据表示\",\"指令采用硬联逻辑实现还是微程序实现\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127261,
			"title": "多处理机上两个程序段之间若有先写后读的数据相关，则 ( )",
			"options": "[\"可以并行执行\",\"不可能并行\",\"任何情况均可交换串行\",\"必须并行执行\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127262,
			"title": "在系列机中发展一种新型号机器，你认为下列（ ）设想是不行的",
			"options": "[\"新增加字符数据类型和若干条字符处理指令\",\"将中断分级由原来的 4 级增加到 5 级\",\"在 CPU和主存之间增设 Cache 存贮器\",\"将浮点数的下溢处理法由原来的恒置“ 1”法，改为查表舍入法\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127263,
			"title": "在指令的操作码编码方式中，优化实用的编码是（ ）。",
			"options": "[\"Huffman 编码\",\"等长编码\",\"Huffman 扩展编码\",\"BCD码\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127264,
			"title": "动态数据流机最突出的特点是使 ( )",
			"options": "[\"数据流令牌无标号\",\"需要程序记数器来实现\",\"令牌带上标号\",\"同步由门 (Latch) 寄存器来实现\"]",
			"answer": "3",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127265,
			"title": "不能够对向量数据结构提供直接支持的是（ ）数据表示。",
			"options": "[\"向量\",\"堆栈\",\"描述符\",\"A和 C\"]",
			"answer": "2",
			"type": "single",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127266,
			"title": "复杂指令系统计算机， 即机器指令系统变得越来越简单易懂，这就是所谓的 CISC指令系统。",
			"options": "",
			"answer": "-1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127267,
			"title": "在计算机技术中,对本来存在的事物或属性,从某一角度来看又好像不存在的概念称为透明性。",
			"options": "",
			"answer": "1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127268,
			"title": "向后兼容是软件兼容的根本特征,也是系列机的根本特征。",
			"options": "",
			"answer": "1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127269,
			"title": "兼容机:不同厂家生产的、具有相同体系结构的计算机。",
			"options": "",
			"answer": "1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127270,
			"title": "一次重叠中通用寄存器组相关的处理办法有推后读和设置相关通路。",
			"options": "",
			"answer": "1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127271,
			"title": "Cache存储器写操作时，在写入Cache的同时将其写回主存，称这种修改主存块内容的方法为写直达法。",
			"options": "",
			"answer": "1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127272,
			"title": "Amdahl提出的体系结构是指机器语言级程序员所看见的计算机属性。",
			"options": "",
			"answer": "1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127273,
			"title": "Amdahl定律:加快某部件执行速度所获得的系统性能加速比,受限于该部件在系统中所占的重要性。",
			"options": "",
			"answer": "1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127274,
			"title": "“主存-辅存”层次的目的为了弥补主存速度的不足。",
			"options": "",
			"answer": "-1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		},
		{
			"id": 127275,
			"title": "“Cache-主存”层次的目的为了弥补主存容量的不足。",
			"options": "",
			"answer": "-1",
			"type": "charge",
			"hard": 1,
			"explain": "无",
			"regtime": "2021-03-18 10:39:35",
			"last_time": null,
			"iscorrect": 0,
			"user_answer": ""
		}
	]
}